(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the design of wordlines in high density memory integrated circuits.
(2) Background of the Invention and Description of Prior Art
High density memory integrated circuits, in particular dynamic random access memory(DRAM) circuits and non-volatile memory circuits such as flash or read only memory(ROM) contain large rectangular arrays of cells, each of which represents a single bit of memory storage. Digital information is written to and read from these cells by peripheral circuitry which addresses each cell through wordlines and bitlines. In a typical DRAM, each storage cell consists of a polysilicon gate metal oxide silicon field effect transistor (MOSFET) and a capacitor. A wordline comprises a continuous band of gate level polysilicon passing alternately over field oxide and over the channel regions of access MOSFETs in the string of memory cells addressed by the wordline. Switching a voltage signal on the wordline from a low to a high voltage turns the access MOSFETs on (for n-channel MOSFETs) and electrically connects the cell's storage capacitor to a bitline for sensing (i.e. accessing the cell). Switching from the high down to the low voltage ends the access. Hence, taking the wordline from low to high or from high to low is the critical path for cell access times. The performance of the DRAM array is dependent upon the speed with which these voltage transitions take place. That speed in turn depends upon the RC(resistance-capacitance) time constant of the wordline.
In order to achieve high performance, the resistive component R must be as small as possible. As a conductor, polysilicon, even heavily doped, cannot compare with other metals such as for example aluminum. Various silicides were pioneered in DRAM gate polysilicon technology (e.g. WSi.sub.X, TaSi.sub.X, MoSi.sub.X) to reduce the sheet resistance and improve wordline speed. These silicides typically had 8-15 .OMEGA./.quadrature. (ohms per square) sheet resistances. Unfortunately, the much lower sheet resistance in-situ formed silicides/salicides(TiSi.sub.X, and CoSi.sub.X) turned out to be difficult to apply to DRAM wordlines because the high temperature steps involved in DRAM cell formation caused their conductance to degrade.
As requirements on DRAM speeds became more demanding and arrays became larger, the need for reducing the resistivity of wordlines becomes even more important. A solution which has met with considerable success is the strapping of the polysilicon wordlines with bands formed in a superjacent metal level, for example aluminum or tungsten. The selected metallization level may be any wiring level above the polysilicon wordlines except the level used to form bitlines (if metal bitlines are used). Practically, in order to avoid unnecessary interconnections, the next available higher level is preferred.
The sheet resistances of the metal bands are tens to hundreds of m.OMEGA./.quadrature. (milliohms per square) making them very effective in reducing the RC time constant of wordlines. The strapping is accomplished by forming a metal line in a metallization level lying directly over and running parallel with the polysilicon wordline and spaced from it by an insulative layer. Periodic contacts between the lines direct most of the current flow through the low resistance metal lines.
A simple case of wordline strapping in a memory cell array 10 is shown in FIG. 1. In this example the metal lines 12 are formed in a single metallization level, for example a first aluminum level. The metal lines 12 are stitched to underlying polysilicon word lines(not shown) which lie directly below the metal lines 12, by means of interlevel contacts 14. Alternate metal lines 12 are directed to two banks of row decoder circuitry 16, 18 located at either side of the cell array 10. The pitch of the metal lines p.sub.1, is defined as the distance between one point on a line and a corresponding point on an adjacent line, in other words, the periodicity of the lines.
As the density of memory arrays increases the pitch of the wordlines decreases. The corresponding decrease in pitch of the metal lines has also driven a decrease in the design rule for the metal lines. The rate of decrease in the metal line design rule has exceeded the rate of design rule decrease for the polysilicon wordlines. This causes depth of field(DOF) problems in the metal line lithography wherein topographical steps occur between the cell array and the peripheral circuitry. These effects are discussed in an article by Saeki, T., Kasai, N., Itani, T., Nishimoto, S., and Fukuzo, Y. in IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, February 1996, page136ff. A Boosted Dual Wordline(BDWL) design scheme is described which relaxes the design metal design rule and improves the circuit yield. However, the design requires additional sub-wordline drivers and drive lines. Images in the peripheral circuits are governed by looser ground rules than those in the array and are therefore less affected by DOF problems. However, this does not apply to wordlines and bitlines traversing the step from the array to the peripheral circuits.
Mazzali, U.S. Pat. No. 5,644,526 cites a variation of the single metallization strapping method wherein the straps are interrupted on the metallization level such that only portions of the subjacent wordlines are re-enforced by conductive straps. The interruptions are in staggered patterns with the purpose of reducing the incidence of shorts caused by defects. In the effort to reduce the incidence of shorts, wordline speed is sacrificed by reducing the amount of upper level metal conductivity enhancement.
FIG. 2 is a cross sectional representation of a wafer 20 with a portion of the memory cell array 10 along the line 2-2' of FIG. 1. The polysilicon wordline 26 passes alternately over regions of field oxide isolation(FOX) 22 and silicon active area 23. The interlevel contacts 14 form the stitching between the polysilicon wordline 26 and the first level metal line 12 directly above it on the planarized inter level dielectric layer(ILD) 28. The break 30 in the cross section indicates that multiple FOX/active region pairs may be present between the two adjacent contacts 14 of the cross section 2-2'.
The narrow pitch p.sub.1 required of metal level lines formed in a single metal level limits their practical width and thereby limits their resistivity. By stitching the polysilicon wordlines alternatively to two levels of metallization, the pitch can be doubled as is shown in the plan view of FIG. 3. The metal lines 12 are formed in a first metallization level while the lines 24 are formed in a second metallization level. The pitch p.sub.2 on each metallization level is twice the pitch p.sub.1 when only a single metallization level is used. Doubling the pitch allows, not only relaxation of the design rule, but also permits broadening large portions of the lines on each level (broadening not shown), thereby lowering their resistance.
The broadening of the metal lines 12, 24 is not shown in FIG. 3 because the overlap would confuse the plan view. However, the effect can easily be visualized and comprehended in the cross section 4-4' shown in FIG. 4. The lines in the second metallization level 24 overlie a second intermetal dielectric(IMD) layer 30 and access the subjacent polysilicon wordlines 26 through vias 32 and contacts 14. The design rule relaxation is realized in the spacing d.sub.1 between the lines. Stitching polysilicon wordlines to two metallization levels in the manner just described to improving wordline performance has several major drawbacks which relate to their necessity to fit into an existing process.
A first drawback is that both metallization levels must have identical specific resistances in order for the wordlines 12 and 24 to render equivalent performance. The metallization levels available for stitching the wordlines are dictated by the design of the process and often are not identical. For example, the first available level might be tungsten having a resistivity of 300-500 m.OMEGA./.quadrature., while the second metal might be aluminum with a resistivity of 30-60 m.OMEGA./.quadrature..
Another problem with this method is that one of the available metallization levels may not be globally planarized and therefore may not be capable of extending across the boundary between the cell array an the peripheral decoder circuitry because of a step at the boundary. The step height generally exceeds the depth of field required by the high resolution stepper to resolve lines on both sides of the step.
Kim. et.al., U.S. Pat. No. 5,631,183 form wordlines which are folded in half, thereby using a single wide superjacent metal line over the folded gate electrode. The cells in the folded gate string are stitched in pairs to the metal strap. In this arrangement the pitch of the metal lines is half the pitch of the subjacent wordlines and the metal strap is half the overall length of the wordline.
Many modern DRAMs avoid wordline stitching entirely in order to avoid tight metal pitches in the array. Instead they rely on splitting the wordlines into many individually driven sections called sub-wordlines. These sub-wordlines are short enough (e.g. 256 to 1024 cells) so that they do not require stitches to achieve sufficient speed. However, the individual drivers occupy valuable chip area. It is therefore desirable to have as many cells as possible on a given sub-wordline.